This invention is in the field of integrated circuits. Embodiments of this invention are more specifically directed to metal-oxide-semiconductor (MOS) transistors.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. As is fundamental in the art, reduction in the size of physical feature sizes of structures realizing transistors and other solid-state devices enables greater integration of more circuit functions per unit “chip” area, or conversely, smaller chip area consumed for a given circuit function. The capability of integrated circuits for a given cost has greatly increased as a result of this miniaturization trend.
As is fundamental in the art, a MOS transistor ideally conducts very low drain current at gate-to-source voltages below the transistor threshold voltage. Subthreshold leakage current, which is the drain current conducted by a MOS transistor under drain-to-source bias but at gate voltages below the threshold voltage, is generally undesirable in digital circuits, particularly in applications that are sensitive to power consumption, such as mobile devices, implantable medical devices, and other battery-powered systems. In recent years, certain analog circuits, such as voltage reference circuits, implement MOS transistors that are biased in the subthreshold region by design, so as to conduct low levels of current at low power supply voltages, while still providing a stable output reference voltage. In each of these circuit applications, minimal subthreshold conduction is desired.
Another non-ideal characteristic of MOS transistors is referred to in the art as “1/f” noise, or “flicker” noise, referring to frequency-dependent random variations in device drain current. Flicker noise generally appears in MOS transistors under both strong inversion (saturation) and weak inversion (subthreshold). MOS transistor flicker noise appears as deviations of circuit performance from design. For example, flicker noise in the signal processing and communications context appears as phase noise (i.e., random fluctuations in the phase of a periodic signal), or “jitter” when expressed in the time domain. It has been observed that analog circuits with subthreshold-biased MOS transistors are especially susceptible to flicker noise.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature size (e.g., the width of the gate electrode) into the deep sub-micron range. State of the art MOS transistor gate widths are now on the order of one-quarter micron. Especially in these sub-micron devices, subthreshold behavior is degraded by a mechanism commonly referred to as the inverse narrow width effect (“INWE”), in which the threshold voltage becomes lower with narrower channel width. It has been observed that this effect is concentrated at the edges of the transistor channel, specifically at the active-to-field edge underlying the gate electrode.
FIGS. 1a and 1b illustrate the construction of conventional n-channel MOS transistor 2 that is susceptible to the INWE. Transistor 2 is formed at an active region of the surface of semiconductor substrate 4, that active region surrounded by isolation dielectric structure 5. In the plan view of FIG. 1a, source/drain regions 6 are the visible portions of this active region, which also includes the surface of the substrate 4 underlying gate structure 8. Gate structure 8, which is typically formed of polycrystalline silicon, a metal, or a conductive metal compound, overlies gate dielectric 7 (FIG. 1b) at the surface of the active region and extends onto isolation dielectric structure 5. Gate dielectric 7 is typically formed of silicon dioxide, silicon nitride, a combination of the two, or in some cases is formed of a “high-k” material such as hafnium oxide. As fundamental in the art, the channel region of transistor 2 is defined by those locations of the active region underlying gate structure 8 between source and drain regions 6. For this n-channel example, source/drain regions 6 are heavily doped n-type portions at the surface of p-type substrate 4, formed in self-aligned manner relative to gate structure 8. The channel region underlying gate structure 8 remains p-type. In this example, transistor 2 has a wide channel region relative to its channel length, as established by the four segments of gate structure 8 that extend across the active region. These four segments of gate structure 8 are connected in parallel by way of the contiguous end regions overlying isolation dielectric structure 5. As such, alternating ones of the source/drain regions 6 correspond to the source and drain, respectively, of transistor 2. Source/drain conduction in transistor 2 thus travels in a direction perpendicular to the longer axis of gate structure 8, shown in this example by channel CH. Contact locations 9 are shown in FIG. 1a, by way of which overlying metal conductors may contact source/drain regions 6 and gate structure 2 in the conventional manner.
FIG. 1b illustrates the cause of the INWE mechanism in transistor 2, by way of a cross-sectional view taken at the interface between the active region at the surface of substrate 4 and isolation dielectric structure 5, at the edge of the transistor channel underlying gate structure 8. Source/drain current is conducted in a direction into and out of the page of FIG. 1b. In this example, isolation dielectric structure 5 is of the type referred to in the art as shallow trench isolation (STI). STI structures are conventionally formed by etching recesses into the surface of the substrate at selected locations, depositing dielectric material such as silicon dioxide into those etched recesses, and then removing excess deposited dielectric (e.g., by chemical-mechanical polishing) to planarize the surface of the STI structures with the surface of neighboring active regions.
Due to the effects of conventional processes, deviation in the uniformity of gate dielectric 7 can be present at interface IF between the active region and its adjacent isolation dielectric structure 5. FIG. 1b illustrates this deviation in an exaggerated fashion, for purposes of this description. More specifically, a recess into the underlying structure is formed at interface IF, and is filled by gate dielectric 7 and gate structure 8. Gate dielectric 7 is typically locally thin in this recess at interface IF, as compared to the rest of the film. This deviation is often manifest in the electrical characteristics of transistor 2 as a lower conduction threshold, namely a lower threshold voltage and a higher current density for a given gate-to-source voltage, as compared with the rest of the channel of transistor 2. This lower conduction threshold is believed to be due to the thinner gate dielectric 7 at interface IF, and also by the “gate wraparound” effect as gate structure 8 dips into the recess at that location. The lowering of the conduction threshold is also referred to in the art as the “double hump” effect. This effect has been observed to be more prevalent in integrated circuits constructed with STI isolation, as opposed to other isolation techniques (e.g., local-oxidation-of-silicon, or “LOCOS”). Because this edge effect more strongly affects transistors with shorter physical gate width, the resulting degradation in electrical performance is classified as a result of INWE behavior.
In circuit implementations, the premature edge conduction at interface IF between the active region and isolation dielectric structure 5 is reflected in performance degradation in several ways. The increased current density and lower threshold voltage at the channel edge of course appears as a higher level of subthreshold conduction, especially at elevated temperature. Unlike subthreshold conduction in the main portion of the transistor channel, this edge conduction has been observed to have a lower body-effect coefficient than does the main part of the channel. As a result, an increased back-bias applied to the transistor body (i.e., well region in which transistor 2 is formed, or the substrate itself, as the case may be) will reduce the subthreshold conduction in the main part of the channel, but will have a much lesser effect relative to the edge conduction, allowing premature edge conduction to dominate the level of subthreshold conduction of transistor 2 under that bias condition. Analog circuits constructed with transistors with lower conduction threshold at channel edges due to this mechanism also exhibit a high level of flicker noise, especially at low gate voltage and with applied back bias.
Off-state leakage due to the edge effect described above exhibits a relatively high variance over a population of transistors. This large device-to-device variance is somewhat inherent due to nature of this mechanism, in which a significant fraction of the subthreshold channel current is conducting at the poorly controlled channel edge of interface IF. This dominance is particularly evident at subthreshold gate bias and with back bias applied to the body node, as current through the main channel is reduced under those conditions. Processes such as chemical-mechanical planarization (CMP) and wet oxide etch typically have a high process variation, randomize the INWE mechanism and thus cause significant mismatch among the transistors in a given integrated circuit. This device mismatch is especially problematic in those analog circuits that rely on good matching of device characteristics, such as low power bandgap voltage reference circuits, as described in Joly et al., “Temperature and Hump Effect Impact on Output Voltage Spread of Low Power Bandgap Designed in the Sub-threshold Area”, International Symposium on Circuits and Systems (IEEE, May 2011), pp. 2549-52, incorporated herein by reference.
Fabrication techniques addressing the edge conduction effect described above are known in the art. One approach involves the formation of a thicker gate dielectric at the edges of the channel region, at the active-to-isolation interface. The gate dielectric over the rest of the channel away from this edge remains at its nominal thickness for the desired technology. The thicker gate dielectric “fence” at the interface suppresses source-drain conduction along the transistor channel edge, and also can eliminate the “gate wraparound” effect and the resulting enhanced subthreshold conduction. However, fabrication of such a dual gate dielectric structure is significantly more complicated than that for a gate dielectric of a single thickness, involving at least one additional photolithography process as well as an additional etch. Both of the additional lithography and etch processes, besides adding manufacturing cost, also increase process variability among transistors in the same integrated circuit, and from wafer to wafer. Significant chip area is also consumed by this approach, to maintain the original transistor drive characteristics. In many situations, it is in fact difficult to control the extension of the fence into the active region, which is especially costly as the tolerance and controllability of the fence becomes a significant fraction of the active area. As such, the thicker dielectric fence approach is generally not useful at deep submicron widths.
Another known approach addressing the effect of the lower conduction threshold at the active-to-isolation interface is shown in plan view in FIG. 1c. This example of transistor 2′ is referred to in the art as a “ring-FET”, in that its gate structure 8′ has a ring shape in its portion overlying the active region. As such, the bulk of the channel region of transistor 2′ is also in the shape of a ring, with one source/drain region 6s defined as the portion within the interior of ring-shaped gate structure 8′, and the other source/drain region 6d defined as the portion of active region outside of gate structure 8′. This results in a channel region that has no edge at an active-to-isolation interface. Rather, because active-to-isolation interface IF is located at an edge of the active region so as to constitute a potential conduction path between portions of contiguous source/drain region 6d, which is necessarily at a uniform potential, no channel conduction occurs along interface IF that would significantly degrade subthreshold conduction performance, 1/f noise performance, or invoke the other effects described above relative to FIGS. 1a and 1b. However, it has been observed that fabrication of ring-shaped gate structure 8′ is quite difficult, in that the dimensions of polysilicon structures of this shape are not as well-controlled as orthogonal rectangular shapes. For this reason, in the most advanced technologies, the shapes of polysilicon or metal gate structures are restricted to all be either horizontal or vertical (i.e., “north-south” or “east-west” in the layout), precluding ring-shaped gate shapes. Furthermore, it is difficult to derive compact computer models for current conduction in ring-FETs, and those models are not scalable, restricting the flexibility with which variable widths and lengths of MOSFETS can be used during circuit design.
By way of further background, as described in Thakar et al., “High Performance 0.3 um CMOS using I-Line Lithography and BARC”, Digest of Technical Papers, Symposium on VLSI Technology (IEEE, 1995), pp. 75-76, and in Thakar et al., “A Manufacturable High Performance Quarter Micron CMOS Technology Using I-Line Lithography and Gate Linewidth Reduction Etch Process”, Digest of Technical Papers, Symposium on VLSI Technology (IEEE, 1996), pp. 216-17, both incorporated herein by reference, polysilicon gate structures that are patterned and etched with a “hammerhead” structure at their tip ends extending onto field oxide are known in the art, for avoiding narrowing of the polysilicon gate as it passes from the active region onto the adjacent field oxide, and “pull back” of the line end of the gate from the field oxide.